Hardware and Software Implementation Of

Rijndael AES on IXP-2XXX

Term Project - EE-540



The Rijndael block cipher algorithm was chosen by NIST as the new advanced encryption standard (AES). As DES is not regarded as a Standard anymore the industry would now rush into implementing AES for cryptographic implementations on their products. Being the strongest encryption algorithm which never has been broken till now, it comes with overheads like performance. Various hardware implementations for AES exist, but have their own pros & cons and there is lot of work being done in the area to achieve perfection.

Project Modeling:

Software Implementation:

The software module consists of implementing the Advanced Encryption Standard on Intelís IXP 2850. The IXP 2850 consists of two cryptographic units having hardware cores of AES, 3DES and SHA-1. It also consists of a SDK for implementing various functionalities for Network Processing.

Hardware Implementation:

Block diagram:


VHDL Code:

                 Top Level AES Module: AES.vhd

                 S_box: s_box.vhd

                 s_box_4: s_box_4.vhd

                 Inverse s_box: inv_s_box.vhd

                 Round : round.vhd

                 Inverse round: inv_round.vhd

                 Shift Rows : shift_rows.vhd

                 Inverse Shift Rows : inv_shift_rows.vhd

                 Mix Column: mix_column.vhd

                 Inverse Mix Column: inv_mix_column.vhd

                 Forward and reverse Key schedule generator: key_schedule.vhd

                 Control of AES block: control.vhd


Simulation output:

Software Implementation output

Hardware Implementation output

Final Chip Design:

The tools used for chip designing are Cadence Physically Knowledgeable Synthesis (PKS) tool for Synthesis, and System On Chip (SOC) Encounter tool for Place and Route. The synthesis output is shown in figure below.

The schematic view of the synthesized AES block is also available from the PKS tool.


Project Report:

Complete Report.doc